TY - JOUR

T1 - High-performance top-gate thin-film transistor with an ultra-thin channel layer

AU - Yen, Te Jui

AU - Chin, Albert

AU - Gritsenko, Vladimir

N1 - Funding Information: Funding: This research was funded by Ministry of Science and Technology of Taiwan, project no. 107-2221-E-009-092-MY3. Publisher Copyright: © 2020 by the authors. Licensee MDPI, Basel, Switzerland. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.

PY - 2020/11

Y1 - 2020/11

N2 - Metal-oxide thin-film transistors (TFTs) have been implanted for a display panel, but further mobility improvement is required for future applications. In this study, excellent performance was observed for top-gate coplanar binary SnO2 TFTs, with a high field-effect mobility (µFE) of 136 cm2/Vs, a large on-current/off-current (ION/IOFF) of 1.5 × 108, and steep subthreshold slopes of 108 mV/dec. Here, µFE represents the maximum among the top-gate TFTs made on an amorphous SiO2 substrate, with a maximum process temperature of ≤ 400◦C. In contrast to a bottom-gate device, a top-gate device is the standard structure for monolithic integrated circuits (ICs). Such a superb device integrity was achieved by using an ultra-thin SnO2 channel layer of 4.5 nm and an HfO2 gate dielectric with a 3 nm SiO2 interfacial layer between the SnO2 and HfO2 . The inserted SiO2 layer is crucial for decreasing the charged defect scattering in the HfO2 and HfO2 /SnO2 interfaces to increase the mobility. Such high µFE, large ION, and low IOFF top-gate SnO2 devices with a coplanar structure are important for display, dynamic random-access memory, and monolithic three-dimensional ICs.

AB - Metal-oxide thin-film transistors (TFTs) have been implanted for a display panel, but further mobility improvement is required for future applications. In this study, excellent performance was observed for top-gate coplanar binary SnO2 TFTs, with a high field-effect mobility (µFE) of 136 cm2/Vs, a large on-current/off-current (ION/IOFF) of 1.5 × 108, and steep subthreshold slopes of 108 mV/dec. Here, µFE represents the maximum among the top-gate TFTs made on an amorphous SiO2 substrate, with a maximum process temperature of ≤ 400◦C. In contrast to a bottom-gate device, a top-gate device is the standard structure for monolithic integrated circuits (ICs). Such a superb device integrity was achieved by using an ultra-thin SnO2 channel layer of 4.5 nm and an HfO2 gate dielectric with a 3 nm SiO2 interfacial layer between the SnO2 and HfO2 . The inserted SiO2 layer is crucial for decreasing the charged defect scattering in the HfO2 and HfO2 /SnO2 interfaces to increase the mobility. Such high µFE, large ION, and low IOFF top-gate SnO2 devices with a coplanar structure are important for display, dynamic random-access memory, and monolithic three-dimensional ICs.

KW - 3D IC

KW - Brain-mimic

KW - Integrated circuit

KW - Monolithic

KW - SnO

KW - TFT

KW - Thin-film transistor

KW - monolithic

KW - OXIDE

KW - PASSIVATION

KW - INSULATOR

KW - MOBILITY

KW - brain-mimic

KW - thin-film transistor

KW - MOSFETS

KW - SnO2

KW - SYSTEMS

KW - integrated circuit

UR - http://www.scopus.com/inward/record.url?scp=85094570156&partnerID=8YFLogxK

U2 - 10.3390/nano10112145

DO - 10.3390/nano10112145

M3 - Article

C2 - 33126463

AN - SCOPUS:85094570156

VL - 10

SP - 1

EP - 8

JO - Nanomaterials

JF - Nanomaterials

SN - 2079-4991

IS - 11

M1 - 2145

ER -