TY - JOUR

T1 - Exceedingly high performance top-gate p-type sno thin film transistor with a nanometer scale channel layer

AU - Yen, Te Jui

AU - Chin, Albert

AU - Gritsenko, Vladimir

N1 - Funding Information: This research was funded by Ministry of Science and Technology of Taiwan, project no. 107-2221-E-009-092-MY3. Publisher Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. Copyright: Copyright 2021 Elsevier B.V., All rights reserved.

PY - 2021/1

Y1 - 2021/1

N2 - Implementing high-performance n-and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. To achieve these goals, a top-gate transistor is preferred to a conventional bottom-gate structure. However, achieving high-performance top-gate p-TFT with good hole field-effect mobility (µFE) and large on-current/off-current (ION /IOFF) is challenging. In this report, coplanar top-gate nanosheet SnO p-TFT with high µFE of 4.4 cm2 /Vs, large ION /IOFF of 1.2 × 105, and sharp transistor’s turn-on subthreshold slopes (SS) of 526 mV/decade were achieved simultaneously. Secondary ion mass spectrometry analysis revealed that the excellent device integrity was strongly related to process temperature, because the HfO2 /SnO interface and related µFE were degraded by Sn and Hf inter-diffusion at an elevated temperature due to weak Sn–O bond enthalpy. Oxygen content during process is also crucial because the hole-conductive p-type SnO channel is oxidized into oxygen-rich n-type SnO2 to demote the device performance. The hole µFE, ION /IOFF, and SS values obtained in this study are the best-reported data to date for top-gate p-TFT device, thus facilitating the development of monolithic 3D ICs on the backend dielectric of IC chips.

AB - Implementing high-performance n-and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. To achieve these goals, a top-gate transistor is preferred to a conventional bottom-gate structure. However, achieving high-performance top-gate p-TFT with good hole field-effect mobility (µFE) and large on-current/off-current (ION /IOFF) is challenging. In this report, coplanar top-gate nanosheet SnO p-TFT with high µFE of 4.4 cm2 /Vs, large ION /IOFF of 1.2 × 105, and sharp transistor’s turn-on subthreshold slopes (SS) of 526 mV/decade were achieved simultaneously. Secondary ion mass spectrometry analysis revealed that the excellent device integrity was strongly related to process temperature, because the HfO2 /SnO interface and related µFE were degraded by Sn and Hf inter-diffusion at an elevated temperature due to weak Sn–O bond enthalpy. Oxygen content during process is also crucial because the hole-conductive p-type SnO channel is oxidized into oxygen-rich n-type SnO2 to demote the device performance. The hole µFE, ION /IOFF, and SS values obtained in this study are the best-reported data to date for top-gate p-TFT device, thus facilitating the development of monolithic 3D ICs on the backend dielectric of IC chips.

KW - 3D brain-mimicking IC

KW - Monolithic 3D

KW - SnO TFT

KW - monolithic 3D

UR - http://www.scopus.com/inward/record.url?scp=85099241231&partnerID=8YFLogxK

U2 - 10.3390/nano11010092

DO - 10.3390/nano11010092

M3 - Article

C2 - 33401635

AN - SCOPUS:85099241231

VL - 11

SP - 1

EP - 11

JO - Nanomaterials

JF - Nanomaterials

SN - 2079-4991

IS - 1

M1 - 92

ER -