Standard

A 32-channel 840Msps TDC based on Altera Cyclone III FPGA. / Grigoriev, D. N.; Kasyanenko, P. V.; Kravchenko, E. A. et al.

In: Journal of Instrumentation, Vol. 12, No. 8, 08025, 31.08.2017.

Research output: Contribution to journal › Article › peer-review

Harvard

Grigoriev, DN, Kasyanenko, PV, Kravchenko, EA, Shamov, AG & Talyshev, AA 2017, 'A 32-channel 840Msps TDC based on Altera Cyclone III FPGA', Journal of Instrumentation, vol. 12, no. 8, 08025. https://doi.org/10.1088/1748-0221/12/08/C08025

APA

Grigoriev, D. N., Kasyanenko, P. V., Kravchenko, E. A., Shamov, A. G., & Talyshev, A. A. (2017). A 32-channel 840Msps TDC based on Altera Cyclone III FPGA. Journal of Instrumentation, 12(8), [08025]. https://doi.org/10.1088/1748-0221/12/08/C08025

Vancouver

Grigoriev DN, Kasyanenko PV, Kravchenko EA, Shamov AG, Talyshev AA. A 32-channel 840Msps TDC based on Altera Cyclone III FPGA. Journal of Instrumentation. 2017 Aug 31;12(8):08025. doi: 10.1088/1748-0221/12/08/C08025

Author

Grigoriev, D. N. ; Kasyanenko, P. V. ; Kravchenko, E. A. et al. / A 32-channel 840Msps TDC based on Altera Cyclone III FPGA. In: Journal of Instrumentation. 2017 ; Vol. 12, No. 8.

BibTeX

@article{9e18457d2c354053aa8b3c0155a952d4,
title = "A 32-channel 840Msps TDC based on Altera Cyclone III FPGA",
abstract = "In this work we present a newly developed TDC (Time-to-Digital Converter) board in the VME-32 standard. The 32-channel TDC board is based on a single FPGA Altera Cyclone III chip. The main parameters of the TDC are as follows: a resolution of 1.19 ns, a dead time of 4.76 ns, and a maximal time interval of 19 504 ns.",
keywords = "Cherenkov detectors, Data acquisition concepts, Digital electronic circuits, FARICH PROTOTYPE",
author = "Grigoriev, {D. N.} and Kasyanenko, {P. V.} and Kravchenko, {E. A.} and Shamov, {A. G.} and Talyshev, {A. A.}",
year = "2017",
month = aug,
day = "31",
doi = "10.1088/1748-0221/12/08/C08025",
language = "English",
volume = "12",
journal = "Journal of Instrumentation",
issn = "1748-0221",
publisher = "IOP Publishing Ltd.",
number = "8",

}

RIS

TY - JOUR

T1 - A 32-channel 840Msps TDC based on Altera Cyclone III FPGA

AU - Grigoriev, D. N.

AU - Kasyanenko, P. V.

AU - Kravchenko, E. A.

AU - Shamov, A. G.

AU - Talyshev, A. A.

PY - 2017/8/31

Y1 - 2017/8/31

N2 - In this work we present a newly developed TDC (Time-to-Digital Converter) board in the VME-32 standard. The 32-channel TDC board is based on a single FPGA Altera Cyclone III chip. The main parameters of the TDC are as follows: a resolution of 1.19 ns, a dead time of 4.76 ns, and a maximal time interval of 19 504 ns.

AB - In this work we present a newly developed TDC (Time-to-Digital Converter) board in the VME-32 standard. The 32-channel TDC board is based on a single FPGA Altera Cyclone III chip. The main parameters of the TDC are as follows: a resolution of 1.19 ns, a dead time of 4.76 ns, and a maximal time interval of 19 504 ns.

KW - Cherenkov detectors

KW - Data acquisition concepts

KW - Digital electronic circuits

KW - FARICH PROTOTYPE

UR - http://www.scopus.com/inward/record.url?scp=85031048259&partnerID=8YFLogxK

U2 - 10.1088/1748-0221/12/08/C08025

DO - 10.1088/1748-0221/12/08/C08025

M3 - Article

AN - SCOPUS:85031048259

VL - 12

JO - Journal of Instrumentation

JF - Journal of Instrumentation

SN - 1748-0221

IS - 8

M1 - 08025

ER -

ID: 9893726