TY - JOUR

T1 - Development of the ATLAS Liquid Argon (LAr) Calorimeter readout electronics for the HL-LHC

AU - Zhulanov, V.

PY - 2020/8

Y1 - 2020/8

N2 - To meet new trigger and data acquisition (TDAQ) buffering requirements and withstand the high expected radiation doses at the High-Luminosity LHC, the ATLAS Liquid Argon Calorimeter readout electronics will be upgraded. The triangular calorimeter signals are amplified and shaped by analog electronics over a dynamic range of 16 bits, with low noise and excellent linearity. Developments of low-power preamplifiers and shapers in the 130 nm CMOS technology are ongoing to meet these requirements. In order to digitize the analog signals on two gains after shaping, a radiation-hard, low-power 40 MHz 14-bit Analog-to-Digital Converter (ADC) is developed using a pipeline + Successive Approximation Register (SAR) architecture in the 65 nm CMOS technology. Characterization of the prototypes of the front-end components show good promise to fulfill all the requirements. The signals will be sent at 40 MHz to the off detector electronics, where Field-Programmable Gate Arrays (FPGAS) connected through high-speed links will perform energy and time reconstruction through the application of corrections and digital filtering. Reduced data will be sent with low latency to the first level trigger, while the full data will be buffered until the reception of trigger accept signals. The data-processing, control and timing functions will be realized by dedicated boards connected through Advanced Telecommunications Computing Architecture (ATCA) crates.

AB - To meet new trigger and data acquisition (TDAQ) buffering requirements and withstand the high expected radiation doses at the High-Luminosity LHC, the ATLAS Liquid Argon Calorimeter readout electronics will be upgraded. The triangular calorimeter signals are amplified and shaped by analog electronics over a dynamic range of 16 bits, with low noise and excellent linearity. Developments of low-power preamplifiers and shapers in the 130 nm CMOS technology are ongoing to meet these requirements. In order to digitize the analog signals on two gains after shaping, a radiation-hard, low-power 40 MHz 14-bit Analog-to-Digital Converter (ADC) is developed using a pipeline + Successive Approximation Register (SAR) architecture in the 65 nm CMOS technology. Characterization of the prototypes of the front-end components show good promise to fulfill all the requirements. The signals will be sent at 40 MHz to the off detector electronics, where Field-Programmable Gate Arrays (FPGAS) connected through high-speed links will perform energy and time reconstruction through the application of corrections and digital filtering. Reduced data will be sent with low latency to the first level trigger, while the full data will be buffered until the reception of trigger accept signals. The data-processing, control and timing functions will be realized by dedicated boards connected through Advanced Telecommunications Computing Architecture (ATCA) crates.

KW - Calorimeters

KW - Data acquisition concepts

KW - Front-end electronics for detector readout

UR - http://www.scopus.com/inward/record.url?scp=85090922790&partnerID=8YFLogxK

U2 - 10.1088/1748-0221/15/08/C08018

DO - 10.1088/1748-0221/15/08/C08018

M3 - Article

AN - SCOPUS:85090922790

VL - 15

JO - Journal of Instrumentation

JF - Journal of Instrumentation

SN - 1748-0221

IS - 8

M1 - C08018

ER -